Asynchronous Polymorphic Logic Gate Design


Technology # 19-33



The asynchronous polymorphic logic gate design described in this IP disclosure form will allow the same digital circuit to exhibit two distinctive functionalities controlled by the supply voltage. Compared to implementing the two functionalities separately, the polymorphic design is much more efficient and provides unique advantages such as adaptivity and enhanced security.  


Some Target Application(s):


* Cryptographic modules, accelerators, and co-processors in any ICs;

* Computational modules in battery-powered electronic devices;

* Control modules in battery-powered electronic devices;

* Any digital intellectual property (IP) that requires the incorporation of a watermark




* Enhanced security – with internal voltage changes, the same cryptographic circuit can switch between different cryptographic algorithms or different cryptographic keys. External attackers do not have any knowledge about such changes since the supply voltage is internal. Moreover, these circuits are highly resistant to side-channel attacks, hardware Trojan insertion, and reverse engineering;


* Hidden watermarking – for intellectual property (IP) protection, the second functionality of a polymorphic circuit can be used as a watermark that is only known by the IP developer;


* Adaptive to operating conditions – when circuit’s operating conditions change (e.g., temperature), the polymorphic circuits autonomously adapt to such changes and adjust their functionalities to accommodate them.




A logic gate design methodology for incorporating the polymorphic circuit concept into a delay-insensitive asynchronous paradigm, more specifically, Multi-Threshold NULL Convention Logic (MTNCL), in order to create practical digital circuits with two distinctive functionalities controlled by the supply voltage, thereby enabling the practical use of such circuits in commercial and government applications.



This invention/technology is available for licensing.

For interested parties seeking further information, feel free to contact:

Mark Allen Lanoue

Technology Manager / Tech Ventures

University of Arkansas

(479) 575-7243


Patent Information:
For Information, Contact:
Mark Lanoue
Technology Manager
University of Arkansas
Jia Di
Chandler Bernard
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