On-Chip IEC ESD Protection Using Parasitic PNP Devices

Description:

 

Technology #18-31

 

The invention proposes a novel area-efficient rail-based ESD protection structure

 

High speed interface ICs require both IC-level and system level ESD protections due to system exposure to static electricity discharges. On-chip ESD protections for high speed interface ICs are difficult due to the stringent pin requirements. Specifically, the ESD designs for system-level ESD requirements are more challenging because of the high discharge current, limited type of ESD components and narrow protection window. Although system-level stress that reaches ICs will vary according to the board-level components and PCB layout, on-chip IEC ESD protection structure typically requires a tremendous amount of chip area. Therefore, area efficient IEC ESD and low-capacitance HBM ESD protections for high-speed interface ICS are highly desire to improve the robustness and reliability of the circuit design.

 

Application:

 

High speed interface integrated circuits, such as USB3.0 controller ICs, HDMI controller ICs, etc. This new invention will reduce the cost of high-speed interface integrated circuits with system level robustness.

It can be implemented with a wide range of semiconductor technology nodes. This method will also be beneficial to the reliability and robustness of integrated circuits with on-chip electrostatic discharge protections.

 

Advantages:

 

The advantages are easy to implement, compatible with all kinds of technologies. It does not require additional system-level protection, which reducing the area of the printed circuit board and number of the system-level components. It also lowers the total system-level cost. The technology/invention will reduce the cost of high-speed interface Integrated circuits with system-level robustness. It can be implemented with a wide range of

semiconductor technology nodes. The method is also benefit the reliability and robustness of integrated circuits with on-chip electrostatic discharge protections. Furthermore, this method is easy to implement, compatible with all kinds of technologies, does not require additional system level protection, reduces the area of the printed circuit board and number of system-level components and it lowers the total system-level cost.

 

 

Technology:

 

The invention proposes a novel area-efficient rail-based ESD protection structure by utilizing the parasitic bipolar structure (i.e. substrate PNP structure formed between the high-side ESD diode and the chip substrate).

 

_______________________________

 

This invention is available for licensing. For interested parties seeking further information, feel free to contact:

 

Mark Allen Lanoue

Technology Manager / Tech Ventures

University of Arkansas

(479) 575-7243

malanoue@uark.edu

 

Patent Information:
For Information, Contact:
Mark Lanoue
Technology Manager
University of Arkansas
479-575-7243
malanoue@uark.edu
Inventors:
Zhong Chen
Farzan Farbiz
Keywords:
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