Reconfigurable 3D Pixel-Parallel Neuromorphic Architecture for Smart Sensors

Description:

Technology # 18-11

 

An neurotrophic architecture for smart sensors

 

Cameras are used for surveillance and monitoring applications and can capture a substantial amount of image data. The processing of this data is either performed post-priori or at powerful backend servers. These methods may be sufficient for certain groups of applications, but they do not suffice for applications in real-time imaging.  Applications such as autonomous navigation in complex environments or hyper spectral image analysis using cameras on drones require near real-time video and image analysis, sometimes under SWAP (Size Weight and Power) constraints. However, there is an invention that overcomes these challenges. The advantages to this invention are vast: power consumption will be reduced by up to 90%, the design provides speed up in system performance and makes the design applicable to high-speed imaging applications, the XPUs are reconfigurable to adopt different computer vision applications and there is a reduction in redundancy.

 

Application(s):

 

The invention will be used in future camera systems, which are predicted to have billions of pixels, thus large amount of data that cannot be transported to processors before processing. Area of interest would be:

 

* Video surveillance

* Consumer electronic

* Drones and remote sensing.

* Self-driving car Health care

 

 

Advantage(s):

 

* The design is a form of focal plane architecture, where we are bringing the computation closer to the image sensor and which is giving real-time application.

* The design has pixel-parallel architecture, which provides speed-up in system performance and makes the design applicable to high-speed imaging application. 

* The XPUs are reconfigurable to adopt different computer vision applications. The application is subdivided into several parts and XPUs process those parts in parallel maintaining a hierarchy. 

* In the hierarchical processing, every layer of the hierarchy there is a gradual graduation of data volume which reduces redundancy. 

* The third layer is a sequential processor. The design offers a small volume of data to the processor thus we achieve a speedup in the sequential operation.

* The design has different clock speed, all XPUs in the first layer performs parallel with different clock speed and achieves a significant amount of power savings. 

* A number of XPUs in the second layer remain idle and saves a lot of power from that layer.

* The reduction of data volume offers less time for operation in the third layer and thus the third layer is comparatively less power hungry.

 

Technology:

 

A new neurotrophic architecture for smart sensors.  

 

 

___________________________________________ 

This invention/technology is available for licensing.

For interested parties seeking further information, feel free to contact:

Mark Allen Lanoue

Technology Manager / Tech Ventures

University of Arkansas

(479) 575-7243

malanoue@uark.edu

 

Patent Information:
App Type Country Serial No. Patent No. File Date Issued Date Expire Date
Provisional United States 62/661,852 4/24/2018    
For Information, Contact:
Mark Lanoue
Technology Manager
University of Arkansas
malanoue@uark.edu
Inventors:
Christophe Bobda
Pankaj Bhowmik
Md Jubaer Hossain Pantho
Marjan Asadinia
Keywords:
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